KVM Forum 2015

The ARM architecture allows for a wide variety of cache configurations, levels and features. This enables building systems that will optimally fit power/area budgets set for the target application. A consequence of this is that architecturally compliant software has to cater for a much wider range of behaviours. Enter virtualization and nested page tables, KVM and QEMU, IO coherency (or lack thereof), legacy code, and what you thought you understood of the above becomes even more mind boggling. This presentation will give an overview of how caches behave in the ARM architecture, especially in the context of virtualization. It will discuss various challenges that we have seen with KVM and how they have been solved. It will also outline some of the areas where previous assumptions made by the entire KVM software stack break down on architectures that do not mandate full coherency.